Bar-type field effect transistor and method for the production thereof

ABSTRACT

The bar-type field effect transistor consists of a substrate, a bar placed above a substrate and a gate and spacer placed above part of the bar.

DESCRIPTION

The invention relates to a fin field-effect transistor and a method forfabricating a fin field-effect transistor.

Such a fin field-effect transistor and a method for fabricating such afin field-effect transistor are disclosed in [1].

The fin field-effect transistor 200 from [1] has a silicon substrate 201and, on the latter, an oxide layer made of silicon oxide SiO₂ 202 (seeFIG. 2).

A fin 203 made of silicon is provided on a part of the oxide layer 202.A gate 204 of the resulting fin field-effect transistor 200 is arrangedabove a part of the fin 203 and along the entire height of the part ofthe fin.

In the case of the fin field-effect transistor 200 disclosed in [1], thechannel region (not illustrated) can be inverted by charge carriers withthe aid of the gate 204 extending along the side walls 205 of the fin203. The fin 203 forms a source region 206 and a drain region 207.

However, in the case of the fin field-effect transistor 200 disclosed in[1], there is no self-aligned spacer technology for the LDD implantationor HDD implantation in order that the fin 203, which is also referred toas mesa, is highly doped with doping atoms in the source region 206 andin the drain region 207.

This is due, in particular, to the fact that oxide spacers 208 areformed only along the side walls 205 of the fin 203. As a result of theoxide spacers 208 that are present, however, the implantation of themesa 203 is prevented via the side walls 205, and, in addition to thesource region 206 and the drain region 207, the channel region isimplanted with doping atoms. The channel region is not protected by anoxide spacer. This leads to underdiffusion during implantation of thefin field-effect transistor 200 with doping atoms.

Moreover, it is often desirable to keep the source region 206 and thedrain region 207 of the fin 203 freely accessible in order that thedrain region 207 of the fin 203 can be exactly doped in a simple manner.

This is not possible, however, with the fin field-effect transistor 200in accordance with [1] and the corresponding fabrication methoddescribed in [1].

In the context of the invention, a fin field-effect transistor shouldgenerally be understood to mean a field-effect transistor whose sourceand drain extend vertically, also in an uncovered manner, or above aninsulator layer, for example an oxide layer, and which has a gate whichextends partly above the vertically extending region, in particularabove the channel region of the field-effect transistor, and along theside walls of the resulting vertical structure. The channel regionextends along the vertical structure from source to drain.

Consequently, the invention is based on the problem of specifying a finfield-effect transistor in which underdiffusion in the channel regionbelow the gate in the context of implanting the gate with doping atomsis avoided.

Furthermore, the invention is based on the problem of specifying methodsfor fabricating such a fin field-effect transistor.

The problems are solved by the fin field-effect transistor and also bythe methods for fabricating the fin field-effect transistor having thefeatures in accordance with the independent patent claims.

A fin field-effect transistor has a substrate, a fin above the substrateand a gate and a spacer above a part of the fin.

In a method for fabricating a fin field-effect transistor, a fin isformed on a substrate. A gate layer is formed above the substrate andabove a part of the fin. An insulation layer is subsequently formedabove the gate layer. The gate layer is partly removed below theinsulation layer and a spacer is formed in the partly removed region.

In a further method for fabricating a fin field-effect transistor, a finis formed above a substrate. A gate layer is formed above the substrate,along and above a part of the fin. An insulation layer is formed abovethe gate layer. Above the region which is not covered by the gate layer,a layer to be etched away is formed up to a height which lies above thefin and below the insulation layer. A spacer is formed above a part ofthe layer to be etched away and the layer to be etched away isessentially removed except for the part which lies directly below thespacer.

A fin field-effect transistor with a spacer produced in accordance witha self-aligned process is specified for the first time by the invention.In the case of the fin field-effect transistor according to theinvention, the spacer is formed above a part of the fin, therebyavoiding underdiffusion during source and drain implantation with dopingatoms.

Moreover, in the case of the fin field-effect transistor according tothe invention, the source region and the drain region of the fin remainfreely accessible, thereby enabling exact and simple doping of thesource region and of the drain region of the fin.

Preferred developments of the invention emerge from the dependentclaims.

The refinements described below refer both to the fin field-effecttransistor and to the methods for fabricating the fin field-effecttransistor.

The gate and/or the spacer may extend essentially along the entireheight of the part of the fin.

The substrate may have silicon, and, as an alternative, it is alsopossible to provide on the substrate a further layer, for example madeof silicon oxide, generally made of an oxide on which the fin and alsothe gate are arranged.

The fin may have silicon.

In accordance with one refinement of the invention, the gate haspolysilicon. Furthermore, the gate may also be formed by a stack ofpolysilicon and tungsten silicide.

The spacer may have silicon oxide and/or silicon nitride.

In accordance with a further refinement of the invention, the spacer hasa first spacer part with silicon oxide and a second spacer part withsilicon nitride. The second spacer part is arranged above the firstspacer part.

In accordance with a further refinement of the invention, an etchingstop layer is provided between the substrate and the fin and the gate.The etching stop layer preferably has silicon nitride.

This refinement results in a further simplification of the method forfabricating the fin field-effect transistor since there is no need foractive monitoring during the etching of the polysilicon layer—formingthe gate—at the boundary with the substrate or the oxide. The etchingprocess is automatically stopped at the etching stop layer in accordancewith this refinement.

Furthermore, the height of the spacer with respect to the substrate maybe essentially equal to the height of the gate.

Underdiffusion during the implantation of the source region and drainregion of the fin field-effect transistor is practically completelyavoided by virtue of this refinement.

At least some of the elements of the fin field-effect transistor may beformed by means of deposition.

Consequently, in accordance with this development, customarysemiconductor process technology can be used, thereby enabling a simpleand cost-effective realization of the fabrication methods.

The layer to be removed may be removed by means of etching, for exampleby means of dry etching or wet etching.

Exemplary embodiments of the invention are illustrated in the figuresand are explained in more detail below.

In the figures:

FIG. 1 shows a fin field-effect transistor in accordance with a firstexemplary embodiment of the invention;

FIG. 2 shows a fin field-effect transistor in accordance with the priorart;

FIG. 3 shows a plan view of the fin field-effect transistor from FIG. 1with a section line A-A′;

FIGS. 4A to 4E show sectional views of the fin field-effect transistorfrom FIG. 1 along the section line A-A′ from FIG. 3, illustrating theindividual method steps of the method for fabricating the finfield-effect transistor from FIG. 1 in accordance with a first exemplaryembodiment of the invention;

FIG. 5 shows a fin field-effect transistor in accordance with a secondexemplary embodiment of the invention;

FIG. 6 shows a plan view of the fin field-effect transistor from FIG. 5with a section line B-B′;

FIGS. 7A to 7E show sectional views of the fin field-effect transistorfrom FIG. 5 along the section line B-B′ from FIG. 6, illustrating theindividual method steps of the method for fabricating the finfield-effect transistor from FIG. 6 in accordance with a secondexemplary embodiment of the invention;

FIG. 8 shows a fin field-effect transistor in accordance with a thirdexemplary embodiment of the invention.

FIG. 1 shows a fin field-effect transistor 100 in accordance with afirst exemplary embodiment of the invention.

The fin field-effect transistor 100 has a substrate 101, on which anoxide layer 102 made of silicon oxide SiO₂ having a layer thickness ofapproximately 200 nm is deposited (cf. FIG. 1). A fin 103 made ofsilicon is formed on the oxide layer 102. In accordance with theexemplary embodiment, a method known from SOI technology (SOI: Siliconon Isolator) is used to fabricate the fin 103. A polysilicon layer 106forming a gate 104 and also spacers 107, 108 made of silicon oxide arearranged above a partial region of the fin 103 and along the partialregion in the vertical direction along the side walls 105 of the fin 103and in the corresponding linearly continued region on the oxide layer102.

A protective layer 111 made of silicon nitride Si₃N₄ for protecting thegate 104 is applied above the gate 104 and the spacers 107, 108. Asource region 109 and a drain region 110 are thus formed, which can beconductively coupled to one another via a channel region (notillustrated) depending on the control by means of the gate 104.

Hereinafter the same reference symbols are used for identical elementsin different drawings.

FIG. 3 shows the fin field-effect transistor 100 from FIG. 1 in planview.

FIG. 3 illustrates a section line A-A′, along which a section is takenwhich produces the sectional views of the fin field-effect transistor100 from FIG. 1 which are illustrated in FIG. 4A to FIG. 4E.

The individual method steps for fabricating the fin field-effecttransistor 100 in accordance with the first exemplary embodiment areexplained below with reference to FIG. 4A to FIG. 4E.

The starting point is an SOI wafer, i.e. clearly a silicon substrate 101in which a silicon oxide layer 102 is situated (cf. FIG. 4A).

In a first step, the threshold voltage of the fin field-effecttransistor 100 is set by the implantation of doping atoms, with boronatoms in accordance with the exemplary embodiment. In the case of afully depleted transistor, it is also possible to omit this channelimplantation in the context of the method.

In a further step, photoresist is applied to the silicon layer formed,in such a way that the photoresist indicates where the fin 103 isintended to be formed.

In a further step, the silicon which is not covered with photoresist isetched by means of a wet etching method or a dry etching method.

The etching method is stopped as soon as the surface of the siliconoxide layer 102 is reached.

In a further step, the photoresist is removed from the fin 103 nowproduced.

In a further step, gate oxide is formed along the side walls of the fin103 and also above the fin 103.

In a further step, a layer of polysilicon is deposited above the siliconoxide layer 102, along the side walls of the fin 103 and also above thefin 103, by means of a CVD method. During the deposition of thepolysilicon, the resulting polysilicon layer is doped with phosphorusatoms or boron atoms.

In a further step, a silicon nitride layer (Si₃N₄) is deposited, bymeans of a CVD method, as a protective layer 111 on the polysiliconlayer which serves as gate 104 in the fin field-effect transistor 100.

Photoresist is subsequently applied on the silicon nitride layer 107 insuch a way that, by virtue of the photoresist, the region which is laterintended to be used as gate 104 and spacers 105, 106 is not etched infurther etching steps.

In a subsequent step, the silicon nitride layer 111, which is notcovered with photoresist, is etched by means of a wet etching method ora dry etching method.

Furthermore, the polysilicon layer 106, which is not protected by thephotoresist is etched away by means of a dry etching method or a wetetching method.

The etching method is ended at the surface of the silicon oxide layer102, so that oxide is not etched.

The photoresist is subsequently removed from the silicon nitride layer111 (cf. FIG. 4B).

In a further step (cf. FIG. 4C), the polysilicon layer 160 is partlyetched away below the silicon nitride layer 111 by means of wet etchingor dry etching. Consequently, a T-shaped structure 400 is clearlyproduced.

In a further step (cf. FIG. 4D), a silicon oxide layer having athickness of approximately 500 nm is deposited by means of a CVD method.

The silicon oxide layer is subsequently removed again by means of achemical mechanical polishing method until the silicon nitride layer 111is reached. Once the silicon nitride layer 111 has been reached, the CMPmethod is stopped.

Silicon oxide is subsequently etched as far as the surface of thesilicon oxide layer 102 by means of a dry etching method. The dryetching is selective with respect to silicon nitride.

The desired spacers 105, 106 of the fin field-effect transistor 100which are illustrated in FIG. 1 are thus formed below the siliconnitride layer but above the fin 103 and on the side walls of the fin andon the silicon oxide layer 102 (cf. FIG. 4D).

In a further step (cf. FIG. 4E), screen oxide is deposited and thesource region and the drain region of the fin 104 are n⁺-implanted viathe side walls of the fin 103, which are now uncovered.

Moreover, implantation of atoms into the channel region is now notpossible since the entire gate 104 is completely protected by thespacers 105, 106.

In concluding standard semiconductor process steps, contacts for gate,source and drain can be etched for the fin field-effect transistor 100,and siliciding of the fin field-effect transistor 100 is possible.

FIG. 5 shows a fin field-effect transistor 500 in accordance with asecond exemplary embodiment of the invention.

In the case of the fin field-effect transistor 500, it is no longernecessary to undercut the polysilicon layer 106 in order to fabricatesaid transistor, as is explained below.

Consequently, the fin field-effect transistor 500 in accordance with thesecond exemplary embodiment is particularly suitable for semiconductorstandard processes.

The fin field-effect transistor 500 in accordance with the secondexemplary embodiment differs from the fin field-effect transistor 100 inaccordance with the first exemplary embodiment essentially by the factthat the silicon nitride layer 107 essentially lies only above thepolysilicon layer of the gate 104, and that two silicon nitride spacers501, 502 are arranged above the spacers 107, 108.

FIG. 6 shows the fin field-effect transistor 500 from FIG. 5 in planview with the section line B-B′, along which the sectional views of FIG.7A to FIG. 7E of the fin field-effect transistor 500 are produced.

FIG. 7A shows the fin field-effect transistor 500 in accordance with thesecond exemplary embodiment in the sectional view along the section lineB-B′ from FIG. 6 with the substrate 101, the silicon oxide layer 102 andthe fin 103 and also a silicon nitride layer 701 on the fin 103.

It is optionally possible, in a further step, to carry out a chargecarrier implantation for the purpose of setting the threshold voltage ofthe fin field-effect transistor 500.

In a further step, gate oxide is formed above the fin and the siliconnitride layer 701.

In a further step (cf. FIG. 7B), a polysilicon layer is deposited bymeans of a suitable CVD method, the polysilicon layer 106 being dopedwith phosphorus atoms or boron atoms during the deposition process. Thepolysilicon layer 106 has a thickness of approximately 400 nm.

In this connection, it should be noted that the thickness of thepolysilicon layer 106 does not constitute a critical criterion in thecontext of the fabrication methods.

After the polysilicon has been removed by means of a chemical mechanicalpolishing method to such an extent as to produce the height of astructure which finally forms the gate 104 of the fin field-effecttransistor 100, a silicon nitride layer 111 as a protective layer isdeposited on the polysilicon layer 106 by means of a CVD method (cf.FIG. 7B).

Afterwards, photoresist is applied to the region provided for the gate104 of the fin field-effect transistor 500, and that part of the siliconnitride layer 702 which is not covered with the photoresist is etchedaway by means of a dry etching method or a wet etching method.

The regions of the polysilicon layer 106 which are not protected by thephotoresist are also etched away by means of a dry etching method or awet etching method. This etching is selective with respect to siliconnitride.

The etching method is stopped at the surface of the silicon nitridelayer 701.

The photoresist is subsequently removed again from the silicon nitridelayer 111 (cf. FIG. 7B).

In a further step, a silicon oxide layer 702 having a thickness ofapproximately 500 nm is deposited, by means of a suitable CVD method,above the fin 103, on the silicon nitride layer 701 of the fin 103 andalso above the remaining surface regions of the fin field-effecttransistor 500 which were uncovered until then.

The silicon oxide is removed by means of a chemical mechanical polishingmethod, the CMP method being stopped at the upper boundary of thesilicon nitride layer 111 arranged on the polysilicon layer 106.

Afterwards, the silicon oxide layer 702 is etched anisotropically as faras the lower edge of the silicon nitride layer 111 situated on thepolysilicon layer 106 (cf. FIG. 7C).

Afterwards, a silicon nitride layer having a thickness of 50 nm inaccordance with the exemplary embodiment, where it should be noted thatthe thickness of the silicon nitride layer can be predetermined in ahighly variable manner, is deposited by means of a suitable CVD method.

In a further step, the silicon nitride spacers 501, 502 (cf. FIG. 7C)are etched by means of a dry etching method.

In a final step, the silicon oxide layer 702 on the silicon nitridelayer 701 is etched away by means of a dry etching method, as a resultof which silicon oxide spacers 107, 108 are formed (cf. FIG. 7D).

In a further step (cf. FIG. 7E), screen oxide is deposited and thesource region and the drain region of the fin 104 are n⁺-implanted viathe side walls of the fin 103, which are now uncovered.

The result is the fin field-effect transistor 500, in which, once againin further method steps, the contacts to source, gate and drain can beetched or which can be subjected to a customary semiconductor standardprocess for further treatment. Siliciding of the fin field-effecttransistor 500 in accordance with the second exemplary embodiment isalso possible.

FIG. 8 shows a fin field-effect transistor 800 in accordance with athird exemplary embodiment.

The fin field-effect transistor 800 in accordance with the thirdexemplary embodiment essentially corresponds to the fin field-effecttransistor 100 in accordance with the first exemplary embodiment, withthe difference that a silicon nitride layer 801 is provided as anetching stop layer on the silicon oxide layer 102. Furthermore, afurther silicon oxide layer 802 is provided on the silicon nitride layer801.

The etching stop layer 801 obviates the need for “etching to time” ofthe last etching method step in each case as far as the surface of thesilicon oxide layer 102, since each etching process is automaticallystopped at the etching stop layer 801.

As an alternative, polysilicon can be used for an etching stop layer801, as also constitutes the silicon nitride layer 702 in accordancewith the second exemplary embodiment above the silicon oxide layer 102.

The fabrication process for the fin field-effect transistor 800 inaccordance with the third exemplary embodiment likewise essentiallycorresponds to the fabrication process for the fin field-effecttransistor 100 in accordance with the first exemplary embodiment,although the further silicon oxide layer 802 is deposited on the siliconnitride layer 801 by means of a CVD method. After correspondingpreparation of the polysilicon layer with photoresist, the furthersilicon oxide layer 802 is etched anisotropically by means of a dryetching method or a wet etching method. The etching is ended on thesilicon nitride layer 801.

It should be pointed out that another exemplary embodiment makesprovision for providing the fin field-effect transistor 500 inaccordance with the second exemplary embodiment without the etching stoplayer 701, in which case the respective etching methods have to bestopped “manually” at the surface of the silicon oxide layer 102.

Furthermore, it should be noted that, instead of the CVD methods, it isalso possible to use sputtering methods or vapor deposition methods, ineach case also in combination with one another.

The following publication is cited in this document:

[1] D. Hisamoto et al, A Fully Depleted Lean-Channel Transistor(DELTA)—A novel vertical ultrathin SOI MOSFET, IEEE Electron DeviceLetters, Volume 11, No. 1, pp. 36-38, 1990

1. A fin field-effect transistor, comprising: a substrate; a fin abovethe substrate, the fin comprising a source region, a channel region anda drain region; a gate oxide formed along side walls of the fin andabove the fin; and a gate and a spacer above the channel region of thefin, wherein the spacer is formed on side walls of the gate andseparately from the gate oxide, wherein the side walls of the fin in thesource region and in the drain region are uncovered from the spacer forimplantation of the source region and the drain region of the fin withdoping atoms.
 2. The fin field-effect transistor as claimed in claim 1,in which the gate and the spacer extend essentially along the entireheight of the part of the fin.
 3. The fin field-effect transistor asclaimed in claim 1, in which the substrate has a layer of silicon oxideprovided above the substrate.
 4. The fin field-effect transistor asclaimed in claim 1, in which the fin has silicon.
 5. The finfield-effect transistor as claimed in claim 1, in which the gate haspolysilicon.
 6. The fin field-effect transistor as claimed in claim 1,in which the spacer comprises silicon oxide and/or silicon nitride. 7.The fin field-effect transistor as claimed in claim 1, in which thespacer has a first spacer part with silicon oxide and a second spacerpart with silicon nitride, the second spacer part being arranged abovethe first spacer part.
 8. The fin field-effect transistor as claimed inclaim 1, in which an etching stop layer is provided between thesubstrate and the fin and the gate.
 9. The fin field-effect transistoras claimed in claim 8, in which the etching stop layer has siliconnitride.
 10. The fin field-effect transistor as claimed in claim 1, inwhich the height of the spacer with respect to the substrate isessentially equal to the height of the gate.